W9425G8EH Datasheet, PDF (48/53 Pages) Winbond – 8M × 4 BANKS × 8 BITS DDR SDRAM

W9425G8EH
11.19 2 Bank Interleave Read Operation (CL = 2, BL = 2)
∗ tCK = 100 MHz
CLK
CLK
tRRD
tRC(a)
tRC(b)
tRRD
CMD
ACTa
ACTb
READAa
READAb ACTa
ACTb
tRCD(a)
tRAS(a)
tRCD(b)
tRAS(b)
tRP(a)
tRP(b)
DQS
DQ
Preamble Postamble Preamble
CL(a)
CL(b)
Postamble
Q0a Q1a
Q0b Q1b
ACTa/b : Bank Act. CMD of bank a/b
READAa/b : Read with Auto Pre.CMD of bank a/b
APa/b : Auto Pre. of bank a/b
APa
APb
11.20 2 Bank Interleave Read Operation (CL = 2, BL = 4)
CLK
CLK
CMD
ACTa
tRRD
tRC(a)
tRC(b)
ACTb READAa
READAb
tRCD(a)
tRAS(a)
tRCD(b)
tRAS(b)
tRP(a)
ACTa
tRRD
tRP(b)
ACTb
DQS
DQ
Preamble
CL(a)
CL(b)
Postamble
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
ACTa/b : Bank Act. CMD of bank a/b
READAa/b : Read with Auto Pre.CMD of bank a/b
APa/b : Auto Pre. of bank a/b
APa
APb
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Publication Release Date: Jul. 04, 2008
Revision A01