W83626F Datasheet, PDF (8/34 Pages) Winbond – LPC-to-ISA Bridge

LPC TO ISA BRIDGE SET
W83626F/W83626D
PRELIMINARY
ISA Interface Signals , continued
SYMBOL PIN
I/O
FUNCTION
MEMCS16# 12
INt Memory Chip Select 16. MEMCS16# asserted indicates that the
memory slave supports 16-bit accesses.
IOCHCK#
76
INt
I/O Channel Check. IOCHK# can be driven by any resource on
the ISA bus during on detection of an error.
OWS#
81
INt Zero Wait States. An ISA slave asserts ZEROWS# after its
address and command signals have been decoded to indicate that
the current cycle can be executed as an ISA zero wait state cycle.
ZEROWS# has no effect during 16-bit I/O cycles.
LA[23:17]
103-1
04
106-1
09
111
OUT24
Unlatched Address. The LA[23:17] address lines are
bi-directional. These address lines allow accesses to physical
memory on the ISA Bus up to 16 Mbytes. LA[23:17] are outputs
when the W83628F owns the ISA Bus.
SMEMW#
82 OUT24 Standard Memory Write. SMEMW# asserted indicates the
current ISA bus cycle is a memory write cycle to an address below
1 Mbyte.
SMEMR#
83 OUT24 Standard Memory Read. SMEMR# asserted indicates the
current ISA bus cycle is a memory read cycle to an address below
1 Mbyte.
REFRESH# 91 OUT24 Refresh. REFRESH# asserted indicates that a refresh cycle is in
progress, or that an ISA master is requesting W83626F to
generate a refresh cycle. Upon PCIRST#, this signal is tri-stated.
BALE
101 OUT24 Bus Address Latch Enable. BALE is an active high signal
asserted by the W83626F to indicate that the address (SA[19:0],
LA[23:17]) and SBHE# signal lines are valid.
The LA[23:17] address lines are latched on the trailing edge of
BALE. BALE remains asserted throughout DMA and ISA master
cycles. BALE is driven low upon PCIRST#.
SBHE#
102 OUT24 System Byte High Enable. SBHE# asserted indicates that a byte
is being transferred on the upper byte (SD[15:8]) of the data bus.
SBHE# is at an unknown state upon PCIRST#.
MEMR#
112 OUT24 Memory Read. MEMR# asserted indicates the current ISA bus
cycle is a memory read.
MEMW#
113 OUT24 Memory Write. MEMW# asserted indicates the current ISA bus
cycle is a memory write.
MASTER# 123
INt MASTER#. This signal is used with a DREQ line by an ISA master
to gain control of the ISA Bus.
RTCEN#
IRQ3
RTC Function Enable.The pin applies a pull-down resistor (4.7K
ohm) to enable RTC functions ( RTCCS#,and IRQ8)
98
INt Parallel Interrupt Requested Input 3.
Publication Release Date: Feb 2000
-6-
Revision 0.50