W83626F Datasheet, PDF (6/34 Pages) Winbond – LPC-to-ISA Bridge

LPC TO ISA BRIDGE SET
W83626F/W83626D
1. PIN DESCRIPTION
I/O12t
I/O24t
I/O12tp3
I/O24tp3
I/OD12t
I/O24t
OUT12
OUT24
O12p3
O24p3
OD12
OD24
INcs
INt
INtd
INtu
INts
INtsp3
- TTL level bi-directional pin with 12 m A source-sink capability
- TTL level bi-directional pin with 24 m A source-sink capability
- 3.3V TTL level bi-directional pin with 12 m A source-sink capability
- 3.3V TTL level bi-directional pin with 24 m A source-sink capability
- TTL level bi-directional pin open drain output with 12 m A sink capability
- TTL level bi-directional pin with 24 m A source-sink capability
- TTL level output pin with 12 m A source-sink capability
- TTL level output pin with 24 m A source-sink capability
- 3.3V TTL level output pin with 12 m A source-sink capability
- 3.3V TTL level output pin with 24 m A source-sink capability
- Open-drain output pin with 12 m A sink capability
- Open-drain output pin with 24 m A sink capability
- CMOS level Schmitt-trigger input pin
- TTL level input pin
- TTL level input pin with internal pull down resistor
- TTL level input pin with internal pull up resistor
- TTL level Schmitt-trigger input pin
- 3.3V TTL level Schmitt-trigger input pin
PRELIMINARY
W83626F PIN DESCRIPTION
LPC Interface
SYMBOL PIN
I/O
FUNCTION
LAD[3:0]
16-19 I/O_12tp3 These signal lines communicate address, control and data
information over the LPC bus between a host and a peripheral.
LFRAME#
PCICLK
13 IN_tsp3 Indicates start of a new cycle or termination of a broken cycle.
PCICLK provides timing for all transactions on the LPC bus. All
21
INt
LPC signals are sampled on the rising edge of PCICLK, and all
timing parameters are defined with respect to this edge.
PCIRST#
14 INtsp3 Reset signal. It can connect to PCIRST# signal on the host.
SERIRQ
LDRQ#
23 I/OD12t Serial IRQ Input/Output.
22 O_12tp3 Encoded DMA Request signal.
Publication Release Date: Feb 2000
-4-
Revision 0.50