W83626F Datasheet, PDF (11/34 Pages) Winbond – LPC-to-ISA Bridge

LPC TO ISA BRIDGE SET
W83626F/W83626D
PRELIMINARY
Clock Buffer and Generator
SYMBOL PIN
I/O
14.318M
14MOUT 1
14MOUT 2
24.576M
25.000M
26
INt
27 OUT12t
28 OUT12t
29 OUT12t
FUNCTION
Main 14.318 MHz Clock Input.
14.318 MHz Buffer Output 1.
14.318 MHz Buffer Output 2.
This pin is weak pull-up during 3 V_DD ramp-up period. The default
setting is 24.576 MHz and selected 25.000 MHz by external
pull-down with 4.7K ohm (recommended) during power ramp-up
period.
24.576 MHz Clock Output for Audio Codec or selected 25.000
MHz Clock Output for LAN on board solution.
Power Signals
SYMBOL
VCC5
VCC3
GND
AVCC3
AGND
PIN
5, 45, 55, 70, 85, 105, 120,
20
15, 50, 60, 80, 95, 110, 125
25
30
I/O
PWR
PWR
PWR
PWR
PWR
FUNCTION
Digital 5V Supply.
Digital 3.3V Supply.
Digital Ground.
Analog 3.3V Supply.
Analog Ground.
Power-on strapping Signals
SYMBOL
PIN
80PCS#/KBEN#
36
ROMCS#
37
MASTER/RTCEN#
123
DACK6#/HEFRAS
128
I/O
I/OD12t
I/OD12t
INt
I/OD24t
FUNCTION
Power-on strapping with
pulled-down register will enable
K/B and mouse functions. When it
is set, pin 38 , 39 and 40 will do
IRQ1, KBCS# and MCCS# signals.
If there is a boot-ROM (BIOS) ,the
signal must power-on with a weak
pulled-high register.
Power-on strapping with
pulled-down register will enable
RTC functions. When it is set, pin
64 and 65 will do IRQ8 and RTCCS#
signals.
Set this function will change the
port that is used to access
configuration-registers . Default
setting is 4Eh ,but by power-on
strapping with a pulled-down
register change to 2Eh.
Publication Release Date: Feb 2000
-9-
Revision 0.50