W83626F Datasheet, PDF (12/34 Pages) Winbond – LPC-to-ISA Bridge

LPC TO ISA BRIDGE SET
W83626F/W83626D
CONFIGURATION REGISTER
1 Chip (Global) Control Register
PRELIMINARY
Enable the following configuration registers by writing 26h to the location 4Eh twice.
Change the location to 2Eh by setting bit4 of CR03 or power-on strapping with a
pulled-down register on pin 128 .
CR03 (ROM Decoder Register, Default , 100011s0b)
Bit 7-5 Reserved.
Bit4
Configure Address and Value
= 0 Write 26h to the location 4E twice. (4Eh and 4Fh are index and data port)
= 1 Write 26h to the location 2E twice(By DACK6 power-on setting with
weak pull-down resistor).(The pair are 2Eh and 2Fh)
Bit 3-2
BIOS Decode Range of High Memory.
= 00 1MB BIOS ROM positive decode.
= 01 2MB BIOS ROM positive decode.
= 10 4MB BIOS ROM positive decode.
= 11 8MB BIOS ROM positive decode. (Default setting)
Bit 1
BIOS ROM decoder Enable.
= 0 Disable BIOS ROM decoder. (Default setting)
=1 Enable BIOS ROM decoder.
Bit 0
BIOS Protected Mode.
=0 BIOS Writed Disable. (Default setting)
=1 BIOS Writed Enable.
This bit set to “ 1 ” for updated BIOS used allow Memory R/W to the range
of BIOS decoded. This bit is always set to “ 0 “ after reset.
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Publication Release Date: Feb 2000
Revision 0.50