W83626F Datasheet, PDF (19/34 Pages) Winbond – LPC-to-ISA Bridge

LPC TO ISA BRIDGE SET
W83626F/W83626D
CR40 (Clock controllable Register , Default 0x00)
PRELIMINARY
This register is used to enable clock power-down state of the chip. It will shut down 14.318MHz.
Bit 7 -1: Reserved.
Bit 0 : =1 Power down mode.When entry power down mode , clock output will be turn off.
=0 Normal used.
CR41 (Clock tested Register , :Reserved for Winbond internal test)
CR42 (Tristate controllable Register(Power-down Mode1) , Default 0x1B)
Bit 7 : REFRESH Cycles Tristated.
Bit 6 : SYSCLK Output Tristated.
Bit 5 : Address Signals Tristated Enable.
Bit 4 - 0 : Defined tristated address signals range.(See Table 1)
For example:
Define address Bit[4..0] = 0x10h
SA [19..16] and LA [23..17] signals will be tristated.
Table 1
Set value(Hex)
Tri_state range
00
SA[19..0] and LA[23..17]
01
SA[19..1] and LA[23..17]
02
SA[19..2] and LA[23..17]
.
.
.
.
Workable
None one
SA[0]
SA[1..0]
.
.
14
Set value(Hex)
.
LA[23..17]
Tri_state range
.
SA[19..0]
Workable
.
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Publication Release Date: Feb 2000
Revision 0.50