W83626F Datasheet, PDF (20/34 Pages) Winbond – LPC-to-ISA Bridge

LPC TO ISA BRIDGE SET
W83626F/W83626D
PRELIMINARY
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1A
LA[23]
SA[19..0] and LA[22..17]
1B
None one
SA[19..0] and LA[23..17]
CR43 (Tristate controllable Register(Power-down Mode2) ,Default 0x07)
The Fast mode is used to improve the performance of transferable interface, because some
applications will do fast transaction . To set the suitable bits to decide on specify range or all ISA cycles
will meet the requested I/O cycles.
Bit 7 : Reserved.
Bit 6 : = 1 Enable Fast mode by ADDRESS DECODER 2 and SYSCLK is depended on
the state of Bit 3 .
= 0 ADDRESS DECORDER 2 doesn’t affect Fast Mode and do original operation.
Bit 5 : = 1 Enable Fast mode by ADDRESS DECODER 1 and SYSCLK is depended on
the state of Bit 3.
= 0 ADDRESS DECORDER 1 doesn’t affect Fast Mode and do original operatio
Bit 4 : = 1 Enable Fast Mode of whole chip, whole ISA cycle of this bridge will be done
Fast Mode operation and SYSCLK is depended on the state of Bit 3.
= 0 Normal operation, just Bit 6 and Bit 5 can affect Fast Mode operation.
Bit 3 : = 1 SYSCLK is equal to PCICLK divided by 1 when decoding range is in Fast Mode.
= 0 SYSCLK is equal to PCICLK divided by 2 when decoding range is in Fast Mode.
Bit 2 : = 1 Disabled Memory cycles.
= 0 Normal used.
Bit 1 : = 1 Forced 16 bit cycles .
= 0 Normal used.
Bit 0 : = 1 8-bit data bus decode only. Only SD [7..0] signals are active.
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Publication Release Date: Feb 2000
Revision 0.50