W83194R-37 Datasheet, PDF (8/19 Pages) Winbond – 100 MHZ AGP CLOCK FOR VIA CHIPSET

Preliminary W83194R-37/-58
W83194R-58 Frequency table selection by software via I²C
SSEL2 SSEL1 SSEL0 Register0 Bit2 CPU SDRAM (MHz)
SSEL3
(MHz) ^{SD_SEL=1 SD_SEL=0}
0
0
0
0
112
112
74.7
0
0
1
0
66.8 66.8
66.8
0
1
0
0
124
124
82.7
0
1
1
0
75
75
75
1
0
0
0
133.3 133.3
88.7
1
0
1
0
83.3 83.3
66.6
1
1
0
0
95.25 95.25
63.5
1
1
1
0
100.2 100.2
66.8
0
0
0
1
103
103
68.7
0
0
1
1
112
112
74.7
0
1
0
1
115
115
76.6
0
1
1
1
120
120
80
1
0
0
1
124
124
82
1
0
1
1
133.3 133.3
66.6
1
1
0
1
140
140
70
1
1
1
1
150
150
75
PCI
(MHz)
37.3
33.4
41.3
37.5
44..3
33.3
31.75
33.4
34.3
37.3
38.3
40
31
33.3
35
37.5
AGP
(MHz)
74.7
66.8
82.7
75
88.7
66.6
63.5
66.8
68.7
74.7
76.6
80
82
66.6
70
75
REF
(MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
FUNCTION TABLE
FUNCTION
DESCRIPTION
TRI-STATE
NORMAL
CPU
Hi-Z
See table
PCI
Hi-Z
See table
OUTPUTS
SDRAM
Hi-Z
CPU
REF
Hi-Z
14.318
8.3.2 Register 1: CPU, 48/24 MHz Clock Register (1 = Active, 0 = Inactive)
BIT @POWERUP
7
1
6
1
5
1
4
1
PIN
-
Reserved
-
Reserved
-
Reserved
-
Reserved
DESCRIPTION
IOAPIC
Hi-Z
14.318
-8-