W83194R-37 Datasheet, PDF (14/19 Pages) Winbond – 100 MHZ AGP CLOCK FOR VIA CHIPSET

Preliminary W83194R-37/-58
9.4.5 Type 5 Buffer for PCICLK(0:4,F)
PARAMETER
Pull-up Current Min.
Pull-up Current Max.
Pull-down Current Min.
Pull-down Current Max.
Rise/Fall Time Min.
Between 0.8V and 2.0V
Rise/Fall Time Max.
Between 0.8V and 2.0V
SYM.
IOH (min.)
IOH (max.)
IOL (min.)
IOL (max.)
TRF (min.)
MIN.
-33
30
0.5
TYP.
MAX.
-33
38
UNITS
mA
mA
mA
mA
nS
TEST CONDITIONS
Vout = 1.0V
Vout = 3.135V
Vout = 1.95V
Vout = 0.4V
15 pF Load
TRF (max.)
2.0
nS 30 pF Load
10.0 POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
CPU_STOP#
1
2
CPUCLK[0:3]
SDRAM
1
2
For synchronous Chipset, CPU_STOP# pin is a synchronous "active low" input pin used to stop the
CPU clocks for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the
CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output
with full pulse width. In this case, CPU "clocks on latency" is less than 2 CPU clocks and clocks off
latency is less then 2 CPU clocks.
- 14 -