W83194R-37 Datasheet, PDF (11/19 Pages) Winbond – 100 MHZ AGP CLOCK FOR VIA CHIPSET

Preliminary W83194R-37/-58
9.0 SPECIFICATIONS
9.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs
must always be tied to an appropriate logic voltage level (Ground or VDD).
PARAMETER
SYMBOL
RATING
Voltage on any pin with respect to GND
VDD, VIN
- 0.5V to +7.0V
Storage Temperature
TSTG
- 65°C to +150°C
Ambient Temperature
TB
- 55°C to +125°C
Operating Temperature
TA
0°C to +70°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
9.2 AC Characteristics
VDDq2 = VDD = VDDq3 = 3.3V ±5%, VDDq2b = 2.375V~2.9V , TA = 0 °C to +70 °C
PARAMETER
SYM. MIN. TYP. MAX. UNITS TEST CONDITIONS
Output Duty Cycle
45 50
55
% Measured at 1.5V
CPU/SDRAM to PCI Offset _tOFF
1
4
nS 15 pF Load Measured at
1.5V
Skew (CPU-CPU), (PCI-
PCI), (SDRAM-SDRAM)
t_SKEW
250
pS 15 pF Load Measured at
1.5V
CPU/SDRAM
t_CCJ
Cycle to Cycle Jitter
±250 pS
CPU/SDRAM
t_JA
Absolute Jitter
500
pS
Jitter Spectrum 20 dB
Bandwidth from Center
BWJ
500 KHz
Output Rise (0.4V−2.0V)
& Fall (2.0V−0.4V) Time
Overshoot/Undershoot
Beyond Power Rails
t_TLH
0.4
t_THL
Vover 0.7
1.6
nS 15 pF Load on CPU and
PCI outputs
1.5
V 22 Ω at source of 8 inch
PCB run to 15 pF load
Ring Back Exclusion
VRBE 0.7
2.1
V Ring Back must not enter
this range.
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Publication Release Date: April 1999
Revision A1