W83194R-37 Datasheet, PDF (15/19 Pages) Winbond – 100 MHZ AGP CLOCK FOR VIA CHIPSET

Preliminary W83194R-37/-58
10.2 PCI_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
PCI_STOP#
PCICLK[0:4]
1
2
1
2
For synchronous Chipset, PCI_STOP# pin is a synchronous "active low" input pin used to stop the
PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock (PCICLK_F). All other clocks will continue to run while
the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output
with full pulse width. In this case, PCI "clocks on latency" is less than 1 PCI clocks and clocks off
latency is less then 1 PCI clocks.
11.0 OPERATION OF DUAL FUCTION PINS
Pins 2, 7, 8, 25 and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Figure 1), therefore,
and are considered input select pins. When VDD reaches 2.5V, the logic level that is present on these
pins are latched into their appropriate internal registers. Once the correct information are properly
latched, these pins will change into output pins and will be pulled low by default. At the end of the
power up timer (within 3 mS) outputs starts to toggle at the specified frequency.
2.5V
V_DD
#2 REF0/CPU3.3#_2.5
#7 PCICLK_F/FS1
#8 PCICLK0/FS2
#25 24/MODE
#26 48/FS0
Output
tri-state
All other clocks
Input
Output
tri-state
Output
pull-low
Within 3 mS
Output
Output
pull-low
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Publication Release Date: April 1999
Revision A1