W83194R-37 Datasheet, PDF (2/19 Pages) Winbond – 100 MHZ AGP CLOCK FOR VIA CHIPSET

Preliminary W83194R-37/-58
3.0 PIN CONFIGURATION
VDD
1
* REF0/CPU3.3#_2.5
2
Vss
3
Xin
4
Xout
5
VDDq3
6
PCICLK_F/*FS1
7
PCICLK0/*FS2
8
Vss
9
PCICLK1
10
PCICLK2
11
PCICLK3
12
PCICLK4
13
VDDq3
14
AGP0
15
Vss
16
CPU_STOP#/SDRAM11
17
PCI_STOP#/SDRAM10
18
VDDq3
19
SDRAM 9
20
SDRAM 8
21
Vss
SDATA
SDCLK
22
23
24
48
VDDq2
47
AGP1
46
REF1/*SD_SEL#
45
Vss
44
CPUCLK0
43
CPUCLK1
42
VDDq2
41
CbPUCLK2
40
CPUCLK3
39
Vss
38
SDRAM 0
37
SDRAM 1
36
VDDq3
35
SDRAM 2
34
SDRAM 3
33
Vss
32
SDRAM 4
31
SDRAM 5
30
VDDq3
29
SDRAM 6
28
SDRAM 7
27
Vss
26
48MHz/*FS0
25
24MHz/*MODE
4.0 BLOCK DIAGRAM
PLL2
~
X1
XTAL
X2
OSC
¡Ò₂
STOP
*FS(0:2) ³
*MODE
CPU3.3#_2.5
*SD_SEL#
CPU_STOP#
PCI_STOP#
*SDATA
*SCLK
PLL1
Spread
Spectrum
STOP
CPU_STOP#
LATCH
~⁵
POR
PCI
clock STOP
Divder
Control
Logic
Config.
Reg.
PCI_STOP#
48MHz
24MHz
REF(0:1
2)
AGP(0:1)
2
CPUCLK(0:3)
4
SDRAM(0:11)
12
3
PCICLK(0:4)
5
PCICLK_F
-2-