W83194R-37 Datasheet, PDF (10/19 Pages) Winbond – 100 MHZ AGP CLOCK FOR VIA CHIPSET

Preliminary W83194R-37/-58
8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive), continued
BIT @POWERUP
PIN
DESCRIPTION
5
x
-
Reserved
4
x
-
Reserved
3
1
17 SDRAM11 (Active/ Inactive)
2
1
18 SDRAM10 (Active/ Inactive)
1
1
20 SDRAM9 (Active/ Inactive)
0
1
21 SDRAM8 (Active/ Inactive)
8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive)
BIT @POWERUP
7
x
6
x
5
x
4
1
3
x
2
x
1
1
0
1
PIN
DESCRIPTION
-
Reserved
-
Reserved
-
Reserved
47 AGP1 (Active/ Inactive)
-
Reserved
-
Reserved
46 REF1 (Active/ Inactive)
2
REF0 (Active/ Inactive)
8.3.7 Register 6: Reserved Register
BIT @POWERUP
7
x
6
x
5
x
4
x
3
x
2
x
1
x
0
x
PIN
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
DESCRIPTION
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