W988D6FB_13 Datasheet, PDF (7/66 Pages) Winbond – 256Mb Mobile LPSDR

W988D6FB / W988D2FB
5. PIN DESCRIPTION
256Mb Mobile LPSDR
5.1 Signal Description
Ball Name
A[n:0]
BA0, BA1
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
CS
RAS
CAS
Function
Address
Bank Select
Description
Multiplexed pins for row and column address.
A10 is Auto Precharge Select
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
Data Input/ Output Multiplexed pins for data output and input.
Chip Select
Row
Address Strobe
Column
Address Strobe
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Command input. When sampled at the rising edge of the clock,
RAS , CAS and WE define the operation to be executed.
Referred to RAS
WE
UDQM / LDQM(x16)
DQM0 ~ DQM3 (x32)
CLK
CKE
VDD
VSS
VDDQ
VSSQ
NC
Write Enable
I/O Mask
Clock Inputs
Clock Enable
Power
Ground
Power for I/O
Buffer
Ground for
I/O Buffer
No Connection
Referred to WE
The output buffer is placed at Hi-Z (with latency of 2 in CL=2, 3;)
when DQM is sampled high in read cycle. In write cycle, sampling
DQM high will block the write operation with zero latency
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE is
low, Power Down mode, Suspend mode or Self Refresh mode is
entered.
Power supply for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Power supply separated from VDD, used for output buffers to
improve noise.
Separated ground from VSS, used for output buffers to improve
noise.
No connection
5.2 Addressing Table
Item
Number of banks
Bank address pins
Auto precharge pin
Row addresses
X16
Column addresses
Row addresses
x32
Column addresses
256 Mb
4
BA0,BA1
A10/AP
A0-A12
A0-A8
A0-A11
A0-A8
-7-
Publication Release Date : August 15, 2013
Revision A01-004