W988D6FB_13 Datasheet, PDF (23/66 Pages) Winbond – 256Mb Mobile LPSDR

W988D6FB / W988D2FB
256Mb Mobile LPSDR
8.1.21 Data Write/Output Enable, Data Mask/Output Disable Command
(DQM = L/H or LDQM, UDQM = L/H or DQM0-3=L/H)
During a Write cycle, the DQM or LDQM, UDQM or DQM0-3 signals mask write data. Each of these signals control the input
buffers per byte. During a Read cycle, the DQM or LDQM, UDQM or DQM0-3 signals control of the output buffers per byte.
I/O Org.
Mask Pin
Masked DQs
LDQM
DQ0~DQ7
× 16
UDQM:
DQ8~DQ15
DQM0:
DQ0~DQ7
DQM1:
DQ8~DQ15
× 32
DQM2:
DQ16~DQ23
DQM3:
DQ24~DQ31
9.OPERATION
9.1 Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after t_RCD from
the Bank Activate command, the data is read out sequentially, synchronized to the positive edges of CLK (a Burst Read operation).
The initial read data becomes available after CAS Latency from the issuing of the Read command. The CAS latency must be
set in the Mode Register at power-up. In addition, the burst length of read data and Addressing Mode must be set. Each bank is
held in the active state unless the Precharge command is issued, so that the sense amplifiers can be used as secondary cache.
When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically after the Read cycle,
then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Also, when the Burst
Length is 1 and t_RCD (min), the timing from the RAS command to the start of the Auto Precharge operation is shorter than t_RAS
(min). In this case, t_RAS (min) must be satisfied by extending t_RCD.
When the Precharge operation is performed on a bank during a Burst Read operation, the Burst operation is terminated.
When the Burst Length is full-page, column data is repeatedly read out until the Burst Stop command or Precharge command is
issued.
9.2 Write Operation
Issuing the Write command after t_RCD from the Bank Activate command, the input data is latched sequentially, synchronizing with
the positive edges of CLK after the Write command (Burst Write operation). The burst length of the Write data (Burst Length) and
Addressing Mode must be set in the Mode Register at power-up.
When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically after the Write cycle,
then the bank is switched to the idle state. This command cannot be interrupted by any other command for the entire burst data
duration. Also, when the Burst Length is 1 and t_RCD (min), the timing from the RAS command to the start of the Auto Precharge
operation is shorter than tRAS (min). In this case, t_RAS (min) must be satisfied by extending t_RCD.
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated.
When the Burst Length is full-page, the input data is repeatedly latched until the Burst Stop command or the Precharge command is
issued.
When the Burst Read and Single Write mode is selected, the write burst length is 1 regardless of the read burst length.
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Publication Release Date : August 15, 2013
Revision A01-004