ISD5100 Datasheet, PDF (57/88 Pages) Winbond – SINGLE-CHIP 1 TO 16 MINUTES DURATION VOICE RECORD/PLAYBACK DEVICES WITH DIGITAL STORAGE CAPABILITY

ISD5100 – SERIES
I²C INTERFACE TIMING
STANDARD-MODE
PARAMETER
SYMBOL
MIN.
MAX.
SCL clock frequency
f_SCL
0
100
Hold time (repeated) START t_HD-STA
4.0
-
condition. After this period, the first
clock pulse is generated
LOW period of the SCL clock
t_LOW
4.7
-
HIGH period of the SCL clock
t_HIGH
4.0
-
Set-up time for a repeated START t_SU-STA
4.7
-
condition
Data set-up time
t_SU-DAT
250
Rise time of both SDA and SCL
t_r
-
signals
-
1000
Fall time of both SDA and SCL
t_f
signals
-
300
Set-up time for STOP condition
t_SU-STO
4.0
-
Bus-free time between a STOP and
t_BUF
4.7
-
START condition
Capacitive load for each bus line
C_b
-
400
Noise margin at the LOW level for
V_nL
0.1 V_DD
-
each connected device (including
hysteresis)
Noise margin at the HIGH level for
V_nH
0.2 V_DD
-
each connected device (including
hysteresis)
FAST-MODE
MIN.
0
0.6
MAX.
400
-
1.3
-
0.6
-
0.6
-
100⁽¹⁾
-
20 + 0.1C_b(2)
300
20 + 0.1C_b(2)
300
0.6
-
1.3
-
-
400
0.1 V_DD
-
0.2 V_DD
-
UNIT
kHz
µs
µs
µs
µs
ns
ns
ns
µs
µs
pF
V
V
1. A Fast-mode I²C-interface device can be used in a Standard-mode I²C-interface system, but the
requirement t_SU;DAT > 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line; t_{r max} + t_SU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I²C -interface specification)
before the SCL line is released.
2. C_b = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times are
allowed.
- 57 -
Publication Release Date: October, 2003
Revision 0.2