W79E201 Datasheet, PDF (53/87 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E201
using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise
rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then
this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks
for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also
detected and shifted into the SBUF.
After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded
and RI is set. However certain conditions must be met before the loading and setting of RI can be
done.
1. RI must be 0 and
2. Either SM2 = 0, or the received stop bit = 1.
If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.
Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to
looking for a 1-to-0 transition on the RxD pin.
Timer 1
Overflow
2
SMOD= _{0 1}
TCLK 0
Timer 2
Overflow
Write to
SBUF
TX START
1
16
TX CLOCK
0
Internal
Data Bus
1
TX SHIFT
TI
RCLK 0 1
16
SERIAL
CONTROLLER ^RI
Transmit Shift Register
STOP
PARIN
START
LOAD
CLOCK
SOUT
TXD
Serial Port
Interrupt
SAMPLE
1-TO-0
DETECTOR
RXD
RX CLOCK
RX START
LOAD
SBUF
RX SHIFT
BIT
DETECTOR
CLOCK
PAROUT
SBUF
SIN
D8
RB8
Receive Shift Register
Read
SBUF
Internal
Data
Bus
Serial Port Mode 1
Mode 2
This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional
description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first),
a programmable 9th bit (TB8) and a stop bit (0). The 9th bit received is put into RB8. The baud rate is
programmable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in
PCON SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at
C1 following the first roll-over of the divide by 16 counter. The next bit is placed on TxD pin at C1
following the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the
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Publication Release Date: December 16, 2004
Revision A2