W79E201 Datasheet, PDF (49/87 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E201
any errant code is executed now, then the reset watchdog timer instructions will not be executed at
the required instants and watchdog reset will occur.
The watchdog time-out selection will result in different time-out values depending on the clock speed.
The reset, when enabled, it will occur 512 clocks after the time-out had occurred.
Table 9. Time-out values for the Watchdog timer
WD1
0
0
1
1
WD0
0
1
0
1
Watchdog
Interval
2¹⁷
2²⁰
2²³
2²⁶
Number of
Clocks
131072
1048576
8388608
67108864
Time
@ 1.8432 MHz
71.11 mS
568.89 mS
4551.11 mS
36408.88 mS
Time
@ 10 MHz
13.11 mS
104.86 mS
838.86 mS
6710.89 mS
Time
@ 25 MHz
5.24 mS
41.94 mS
335.54 mS
2684.35 mS
The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not
disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into
a known state.
The control bits that support the Watchdog timer are discussed below.
Watchdog Control
BIT NAME
FUNCTION
7
-
Reserved.
Power-on reset flag. Hardware will set this flag on a power up condition. This flag
6 POR can be read or written by software. A write by software is the only way to clear
this bit once it is set.
5
-
Reserved.
4
-
Reserved.
Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will
3
WDIF
set this bit to indicate that the watchdog interrupt has occurred. If the interrupt is
not enabled, then this bit indicates that the time-out period has elapsed. This bit
must be cleared by software.
Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer
2
WTRF
causes a reset. Software can read it but must clear it manually. A power-fail reset
will also clear the bit. This bit helps software in determining the cause of a reset. If
EWT = 0, the watchdog timer will have no affect on this bit.
1
EWT
Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer
Reset function.
Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know
state. It also helps in resetting the watchdog timer before a time-out occurs.
0 RWT Failing to set the EWT before time-out will cause an interrupt, if EWDI (EIE.4) is
set, and 512 clocks after that a watchdog timer reset will be generated if EWT is
set. This bit is self-clearing by hardware.
- 49 -
Publication Release Date: December 16, 2004
Revision A2