W79E201 Datasheet, PDF (5/87 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E201
4. PIN DESCRIPTION
SYMBOL
EA
TYPE
IH
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out
of external ROM. It should be kept high to access internal ROM. The ROM
address and data will not be present on the bus if EA pin is high and the
program counter is within 16KB area. Otherwise they will be present on the
bus.
PSEN
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto
O H ^{the Port 0 address/data bus during fetch and MOVC operations. When}
internal ROM access is performed, no PSEN strobe signal outputs from this
pin.
ALE
OH
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0.
RST
IL
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
XTAL1
I
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an
external clock.
XTAL2
O CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS
P Digital GROUND: Ground potential
VDD
P Digital POWER SUPPLY: Supply voltage for operation.
AVDD
P Analog POWER SUPPLY: Supply analog voltage for operation.
AVSS
P GROUND: Analog Ground potential
Vref
P Vref: Analog reference input maximum voltage for ADC
PORT 0: Port 0 is an open-drain bi-directional I/O port with internal pull-up
P0.0−P0.7
I/O D(H)
resister option that is enabled by setting bit 0 of P0R(8Fh) to logic high. This
port also provides a multiplexed low order address/data bus during accesses
to external memory.
P1.0−P1.7
I
PORT 1: Port 1 is an input port. Or with an 8-bit analog input port for ADC0-
ADC7(8 analog input channels) used.
P2.0−P2.7
I/O
PORT 2: Port 2 is a bi-directional I/O port with internal weakly pull-ups. This
port also provides the upper address bits for accesses to external memory.
P3.0−P3.7
I/O
PORT 3: Port 2 is a bi-directional I/O port with internal weakly pull-ups.
Function is the same as that of the standard 8052.
P4.0
I/O PORT 4: A bi-directional I/O port with internal with weakly pull-ups
TCK
I L TCK: JTAG test clock
TMS
I H TMS: JTAG Test Mode select
TDI
I H TDI: JTAG Test Data In
TDO
O TDO: JTAG Test Data Out
* Note: TYPE P: Power, I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain.
Publication Release Date: December 16, 2004
-5-
Revision A2