W9864G6IH Datasheet, PDF (5/43 Pages) Winbond – 1M × 4BANKS × 16BITS SDRAM

W9864G6IH
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
23 ~ 26, 22,
29 ~35
A0−A11
Address
Row address: A0−A11. Column address: A0−A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
20, 21
BS0, BS1 Bank Select
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
Data
DQ0−DQ15
Input/ Output
51, 53
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
19
CS
Chip Select
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
18
RAS
Row Address
Strobe
the clock RAS , CAS and WE define the
operation to be executed.
17
CAS
Column
Address Strobe ^{Referred to RAS}
16
39, 15
38
WE
UDQM
LDQM
CLK
37
CKE
1, 14, 27
VDD
28, 41, 54 VSS
3, 9, 43, 49 VDDQ
6, 12, 46, 52 VSSQ
36, 40
NC
Write Enable _{Referred to RAS}
Input/output
mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
Clock Enable
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power
Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside
DRAM.
Power for I/O Separated power from VDD, to improve DQ noise
buffer
immunity.
Ground for I/O
buffer
No Connection
Separated ground from VSS, to improve DQ noise
immunity.
No connection.(The NC pin must connect to
ground or floating.)
Publication Release Date:Mar. 31, 2008
-5-
Revision A05