W9864G6IH Datasheet, PDF (39/43 Pages) Winbond – 1M × 4BANKS × 16BITS SDRAM

W9864G6IH
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10 11
(1) Read cycle
( a ) CAS latency =2
Command
Read
BST
DQ
( b )CAS latency = 3
Command
Read
DQ
Q0 Q1 Q2 Q3 Q4
BST
Q0 Q1 Q2 Q3 Q4
(2) Write cycle
Command Write
BST
DQ Q0 Q1 Q2 Q3 Q4
Note: BST represents the Burst stop command
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
0
1
2
3
4
5
6
7
8
(1) Read cycle
(a) CAS latency =2
Command
DQ
(b) CAS latency =3
Command
DQ
Read
Read
Q0
Q1
Q0
Q2
Q1
PRCG
Q3
Q4
PRCG
Q2
Q3
Q4
9
10 11
(2) Write cycle
(a) CAS latency =2
Command
DQM
DQ
(b) CAS latency =3
Command
DQM
DQ
Write
Q0
Write
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
tWR
PRCG
tWR
PRCG
Q4
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Publication Release Date:Mar. 31, 2008
Revision A05