W9864G6IH Datasheet, PDF (38/43 Pages) Winbond – 1M × 4BANKS × 16BITS SDRAM

W9864G6IH
11.17 Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) Command
Read Write
DQM
DQ
D0
D1
D2
D3
( b ) Command
DQM
DQ
(2) CAS Latency=3
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
Read
Write
D0
D1
D2
D3
Read Write
D0
D1
D2
D3
Read
Write
D0
D1
D2
D3
Note: The Output data must be masked by DQM to avoid I/O conflict.
11.18 Timing Chart of Write to Read Cycle
In the case of Burst Length = 4
0
1
2
3
4
5
6
7
8
9
(1) CAS Latency = 2
( a ) Command
DQM
DQ
Write Read
D0
Q0
Q1
Q2
Q3
( b ) Command
DQM
DQ
Write
D0 D1
Read
Q0
Q1
Q2
Q3
10 11
(2) CAS Latency = 3
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
Write Read
D0
Write
Read
D0
D1
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
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Publication Release Date:Mar. 31, 2008
Revision A05