W25Q32JVSFIQ-TR Datasheet, PDF (29/78 Pages) Winbond – 3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL, QUAD SPI

W25Q32JV
During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven high,
the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
Refer to section 7.1 for Status Register descriptions.
Figure 9a. Write Status Register-1/2/3 Instruction (SPI Mode)
The W25Q32JV is also backward compatible to Winbond’s previous generations of serial flash memories,
in which the Status Register-1&2 can be written using a single “Write Status Register-1 (01h)” command.
To complete the Write Status Register-1&2 instruction, the /CS pin must be driven high after the sixteenth
bit of data that is clocked in as shown in Figure 9c & 9d. If /CS is driven high after the eighth clock, the Write
Status Register-1 (01h) instruction will only program the Status Register-1, the Status Register-2 will not
be affected (Previous generations will clear CMP and QE bits).
/CS
CLK
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 3
Mode 0
DI
(IO₀)
DO
(IO₁)
* ^{= MSB}
Instruction (01h)
Status Register 1 in
Status Register 2 in
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
*
*
High Impedance
Figure 9c. Write Status Register-1/2 Instruction (SPI Mode)
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Publication Release Date: November 18, 2014
Preliminary-Revision A1