W25Q32JVSFIQ-TR Datasheet, PDF (17/78 Pages) Winbond – 3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL, QUAD SPI

W25Q32JV
Status Register Protect (SRP, SRL)
The Status Register Protect bits (SRP) are non-volatile read/write bits in the status register (S7). The SRP
bit controls the method of write protection: software protection or hardware protection. The Status Register
Lock bits (SRL) are non-volatile/volatile read/write bits in the status register (S8). The SRL bit controls the
method of write protection: temporary lock-down or permanently one time program.
SRP
/WP
Status
Protection
Description
0
X
Software
Protection
/WP pin has no control. The Status register can be
written to after a Write Enable instruction, WEL=1.
[Factory Default]
0
Hardware
Protected
When /WP pin is low the Status Register can’t be
written to.
1
1
Hardware
Unprotected
When /WP pin is high the Status register can be
written to after a Write Enable instruction, WEL=1.
SRL
0
1
Status Register Lock
Description
Non-Lock
Status Register is unlocked
Lock-Down ⁽¹⁾
(temporary/Volatile)
Status Register is locked by standard status register
write command and can’t be written to again until the
next power-down, power-up cycle.
One Time Program⁽²⁾
Status Register is permanently locked by special
(Permanently/Non-Volatile) command flow^* and can’t be written to
Note:
1. When SRL =1, a power-down, power-up cycle will change SRL =0 state.
2. Please contact Winbond for details regarding the special instruction sequence.
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Publication Release Date: November 18, 2014
Preliminary-Revision A1