W25Q32JVSFIQ-TR Datasheet, PDF (12/78 Pages) Winbond – 3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL, QUAD SPI

W25Q32JV
6. FUNCTIONAL DESCRIPTIONS
6.1 Standard SPI Instructions
The W25Q32JV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI
input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO
output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising
edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
6.2 Dual SPI Instructions
The W25Q32JV supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical
code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become
bidirectional I/O pins: IO0 and IO1.
6.3 Quad SPI Instructions
The W25Q32JV supports Quad SPI operation when using instructions such as “Fast Read Quad Output
(6Bh)”, and “Fast Read Quad I/O (EBh). These instructions allow data to be transferred to or from the device
four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant
improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or
execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become
bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI
instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
6.4 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q32JV operation to be paused
while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI
data and clock signals are shared with other devices. For example, consider if the page buffer was only
partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can
save the state of the instruction and the data in the buffer so programming can resume where it left off once
the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation,
not during Quad SPI. The Quad Enable Bit QE in Status Register-2 is used to determine if the pin is used
as /HOLD pin or data I/O pin. When QE=0 (factory default), the pin is /HOLD, when QE=1, the pin will
become an I/O pin, /HOLD function is no longer available.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising
edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition
will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is
high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS)
signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal
logic state of the device.
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