W987D6HBGX6E-TR Datasheet, PDF (28/68 Pages) Winbond – 128Mb Mobile LPSDR

W987D6HB / W987D2HB
128Mb Mobile LPSDR
8.5 Mode Register Operation
The Mode register designates the operation mode for the Read or Write cycle. This register is divided into three fields; A Burst Length
field to set the length of burst data, an Addressing Mode selected bits to designate the column access sequence in a Burst cycle, and a
CAS Latency field to set the access time in clock cycle.
The Mode Register is programmed by the Mode Register Set command when all banks are in the idle state. The data to be set in the
Mode Register is transferred using the A0~An, BA0, BA1 address inputs. The initial value of the Mode Register after power-up is
undefined; therefore the Mode Register Set command must be issued before proper operation.
8.5.1 Burst Length field (A2~A0)
This field specifies the data length for column access using the A2~A0 pins and sets the Burst Length to be 1, 2, 4, 8, words, or full-page.
A2
A1
A0
BUST
LENGTH
0
0
0
1 word
0
0
1
2 words
0
1
0
4 words
0
1
1
8 words
1
1
1
Full-Page
8.5.2 Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential mode. When the A3 bit is 0, Sequential mode is
selected. When the A3 bit is 1, Interleave mode is selected. Both Addressing modes support burst length of 1, 2, 4 and 8 words.
Additionally, Sequential mode supports the full-page burst.
A3
ADDRESSING MODE
0
Sequential
1
Interleave
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Publication Release Date: Jun. 09, 2011
Revision A01-002