W987D6HBGX6E-TR Datasheet, PDF (2/68 Pages) Winbond – 128Mb Mobile LPSDR

W987D6HB / W987D2HB
128Mb Mobile LPSDR
7.1.21 Data Write/Output Enable, Data Mask/Output Disable Command ........................................................... 22
8. OPERATION................................................................................................................................. 22
8.1 Read Operation................................................................................................................................. 22
8.2 Write Operation................................................................................................................................. 22
8.3 Precharge ......................................................................................................................................... 23
8.3.1 Auto Precharge ........................................................................................................................................... 23
8.3.2 READ with auto precharge interrupted by a READ (with or without auto precharge) ................................ 23
8.3.3 READ with auto precharge interrupted by a WRITE (with or without auto precharge) ............................... 24
8.3.4 WRITE with auto precharge interrupted by a READ (with or without auto precharge) ............................... 25
8.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) ............................. 26
8.4 Burst Termination.............................................................................................................................. 27
8.5 Mode Register Operation .................................................................................................................. 28
8.5.1 Burst Length field (A2~A0) .......................................................................................................................... 28
8.5.2 Addressing Mode Select (A3) ..................................................................................................................... 28
8.5.3 Addressing Sequence for Sequential Mode................................................................................................ 29
8.5.4 Addressing Sequence for Interleave Mode ................................................................................................. 29
8.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13)............................................. 30
8.5.6 Read Cycle CAS Latency = 3................................................................................................................... 30
8.5.7 CAS Latency field (A6~A4) ...................................................................................................................... 31
8.5.8 Mode Register Definition ............................................................................................................................. 31
8.6 Extended Mode Register Description ................................................................................................ 32
8.7 Simplified State Diagram................................................................................................................... 33
9. CONTROL TIMING WAVEFORMS .............................................................................................. 34
9.1 Command Input Timing ..................................................................................................................... 34
9.2 Read Timing...................................................................................................................................... 35
9.3 Control Timing of Input Data (x16) .................................................................................................... 36
9.4 Control Timing of Output Data (x16).................................................................................................. 37
9.5 Control Timing of Input Data (x32) .................................................................................................... 38
9.6 Control Timing of Output Data (x32).................................................................................................. 39
9.7 Mode register Set (MRS) Cycle ......................................................................................................... 40
10. OPERATING TIMING EXAMPLE ............................................................................................... 42
10.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)........................................................ 42
10.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge) ............................. 43
10.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)........................................................ 44
10.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge) ............................. 45
10.5 Interleaved Bank Write (Burst Length = 8)....................................................................................... 46
10.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge) ............................................................ 47
10.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ................................................................ 48
10.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ..................................................... 49
10.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3).......................................................... 50
10.10 Auto Precharge Write (Burst Length = 4)....................................................................................... 51
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Publication Release Date: Jun. 09, 2011
Revision A01-002