W987D6HBGX6E-TR Datasheet, PDF (20/68 Pages) Winbond – 128Mb Mobile LPSDR

W987D6HB / W987D2HB
7.1.4 Bank Activate Command
128Mb Mobile LPSDR
( RAS = L, CAS = H, WE = H, BA0, BA1 = Bank, A0~An = Row Address)
The Bank Activate command activates the bank designated by the BS (Bank Select) signal.
Row addresses are latched on A0~An when this command is issued and the cell data is read out to the sense amplifiers. The
maximum time that each bank can be held in the active state is specified as tRAS (max).
7.1.5 Bank Precharge Command
( RAS = L, RAS = H, WE = L, BA0, BA1 = Bank, A10 =L )
The Bank Precharge command is used to close (or precharge) the bank that is activated. Using this command, systems can
designated the bank to be closed by specifying the BS address bit setting in the command set. A Precharge command can be used to
precharge each bank separately (Bank Precharge) or all four banks simultaneously (Precharge All). After the Bank Precharge
command is issued, any one bank can close, and the closed bank transitions from the active state to the idle state. To re-activate the
closed bank, a system has to wait the minimum tRP delay after issuing the Precharge command before issuing the Active Command
for the device to complete the Precharge operation.
7.1.6 Precharge All Command
( RAS = L, CAS = H, WE = L, BA0, BA1 = Don’t care, A10 =H )
The Precharge All command is used to precharge all banks simultaneously. After this command is issued, all four banks close and
transition from the active state to the idle state.
7.1.7 Write Command
( RAS = H, CAS = L, WE = L, BA0, BA1 = Bank, A10 = L )
The Write command initiates a Write operation to the bank selected by BA0 and BA1 address inputs. The write data is latched at the
positive edge of CLK. Users should preprogram the length of the write data (Burst Length) and the column access sequence
(Addressing Mode) by setting the Mode Resister at power-up prior to using the Write command.
7.1.8 Write with Auto Precharge Command
( RAS = H, CAS = L, WE = L, BA0, BA1 = Bank, A10 = H )
The Write with Auto Precharge command performs the Precharge operation automatically after the Write operation. The internal
precharge starts in the cycles immediately following the cycle in which the last data is written independent of CAS Latency.
7.1.9 Read Command
( RAS = H, CAS = L, WE = H, BA0, BA1 = Bank, A10 = L )
The Read command performs a Read operation to the bank designated by BA0-1. The read data is issued sequentially synchronized
to the positive edges of CLK. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS
command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Write operation.
7.1.10 Read with Auto Precharge Command
( RAS = H, CAS = L, WE = H, BA0, BA1 = Bank, A10 =H )
The Read with Auto Precharge command automatically performs the Precharge operation after the Read operation.
When the CAS Latency = 3, the internal precharge starts two cycles before the last data is output. When the CAS
Latency = 2, the internal precharge starts one cycle before the last data is output.
7.1.11 Extended Mode Register Set Command
( RAS = L, CAS = L, WE = L, BA0, BA1, A0~An = Register Data)
The Extended Mode Register Set command is designed to support Partial Array Self Refresh, Temperature Compensated Self
Refresh, and Output Driver Strength/Size by allowing users to program each value by setting predefined address bits. The default
values in the Extended Mode Register after power-up are undefined; therefore this command must be issued during the power-up
sequence. Also, this command can be issued while all banks are in the idle state.
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Publication Release Date: Jun. 09, 2011
Revision A01-002