W741E20X Datasheet, PDF (24/84 Pages) Winbond – 4-BIT FLASH MICROCONTROLLER

Preliminary W741E20X
Interrupt Enable Flag (IEF)
The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used
to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these
interrupts is accepted, the corresponding to the bit of the event flag will be reset, but the other bits are
unaffected. In interrupt subroutine, these interrupts will be disable till the instruction MOV IEF, #I or EN
INT is executed again. To enable these interrupts, the instructions MOV IEF, #I or EN INT must be
executed again. Otherwise, these interrupts can be disable by executing DIS INT instruction. The bit
descriptions are as follows:
76543210
IEF w w w w
www
Note: W means write only.
IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0.
IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0.
IEF.2 = 1 Interrupt 2 is accepted by a signal change at port RC.
IEF.3 is reserved.
IEF.4 = 1 Interrupt 4 is accepted by a falling edge signal at the INT pin.
IEF.5 = 1 Interrupt 5 is accepted by the serial port received completely.
IEF.6 = 1 Interrupt 6 is accepted by the serial port transmitted completely.
IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.
External INT
The external interrupt INT pin contains a pull-up resistor. When the HEF.4 or IEF.4 flag is set, the
falling edge of the INT pin will execute the hold mode release or interrupt subroutine. A low level on
the INT pin will release the stop mode.
Stop Mode Operation
In stop mode, all operations of the µC cease (including the operation of the oscillator). The µC enters
stop mode when the STOP instruction is executed and exits stop mode when an external trigger is
activated (by a low level on the INT pin or a falling signal on the RC port). When the designated signal
is accepted, the µC awakens and warm-up, and then executes the next instruction.
Stop Mode Wake-up Enable Flag for Ports RC (SEF)
The stop mode wake-up flag for ports RC is organized as an 4-bit binary register (SEF.0 to SEF.3).
Before port RC may be used to make the device exit the stop mode, the content of the SEF must be
set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:
3 210
SEF w w w w
Note: W means write only.
SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0
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