W741E20X Datasheet, PDF (17/84 Pages) Winbond – 4-BIT FLASH MICROCONTROLLER

Preliminary W741E20X
Bit 0 = 0 RC.0 works as output pin; Bit 0 = 1 RC.0 works as input pin
Bit 1 = 0 RC.1 works as output pin; Bit 1 = 1 RC.1 works as input pin
Bit 2 = 0 RC.2 works as output pin; Bit 2 = 1 RC.2 works as input pin
Bit 3 = 0 RC.3 works as output pin; Bit 3 = 1 RC.3 works as input pin
At initial reset, port RC is input mode (PM4 = 1111B).
Port Mode 5 Register (PM5)
The port mode 5 register is organized as 4-bit binary register (PM5.0 to PM5.3). PM5 can be used to
control the input/output mode of port RD. PM5 is controlled by the MOV PM5, #I instruction. The bit
descriptions are as follows:
3 210
PM5 w w w w
Note: W means write only.
Bit 0 = 0 RD.0 works as output pin; Bit 0 = 1 RD.0 works as input pin
Bit 1 = 0 RD.1 works as output pin; Bit 1 = 1 RD.1 works as input pin
Bit 2 = 0 RD.2 works as output pin; Bit 2 = 1 RD.2 works as input pin
Bit 3 = 0 RD.3 works as output pin; Bit 3 = 1 RD.3 works as input pin
At initial reset, the port RB is input mode (PM2 = 1111B).
Input/Output Ports RC, RD
Port RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. At initial reset,
input/output ports RC and RD are both in input mode. When RC and RD are used as output ports, the
CMOS type is the only ouput driving type. Each pin of port RC or RD can be specified as input or
output mode independently by the PM4 and PM5 registers. The MOVA R, RC or MOVA R, RD
instructions operate the input functions and the MOV RC, R or MOV RD, R operate the output
functions. When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change at the
specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status register
0 (PSR0) records the status of port RC, and that can be read out and cleared by the MOV R, PSR0,
and CLR PSR0 instructions. Before the port mode of the RC port is changed from output mode to input
mode in the hold mode release and interrupt application, the output value must be preset to the same
as the system status to prevent the undesired signal change being accepted. When the interrupt of RC
port is accepted, the corresponding event flag (EVF.2) will be reset, but the content of PSR0 should not
be changed except the CLR PSR0 or MOV PEF,#I instruction being executed or performing the reset
function. In addition, the falling edge signal on the pin of port RC specified by the instruction MOV SEF,
#I will cause the device to exit the stop mode. The RD port is used as the I/O port only. Refer to Figure
9, Figure 10 and the instruction table for more details.
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Publication Release Date: March 1998
Revision A1