W741E20X Datasheet, PDF (18/84 Pages) Winbond – 4-BIT FLASH MICROCONTROLLER

Preliminary W741E20X
Input/Output Pin of the RC(RD)
Vdd
DATA
BUS
Output
Buffer
Enable
MOV RC, R
(or MOV RD, R)
Instruction
PM4.n
(or PM5.n)
Enable
MOVA R, RC
(or MOVA R, RD)
instruction
I/O PIN
RC.n(RD.n)
Figure 9. Architecture of RC & RD Input/Output Pins
Port Enable Flag (PEF)
The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be
used to release the hold mode or preform interrupt function, the content of the PEF must be set first.
The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:
3 210
PEF w w w w
Note: W means write only.
PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt.
PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt.
PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt.
PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt.
Port Status Register 0 (PSR0)
Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or
cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:
3
2
1
0
PSR0 R
R
R
R
Note: R means read only.
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