TC9WMC1FK Datasheet, PDF (8/16 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuits Silicon Monolithic

TC9WMC1FK/FU,TC9WMC2FK/FU
(3.5)
Erase All (ERASE)
The Erase All instruction writes every bit in the memory array to 1. After the CS is driven High,
a start bit is transferred followed by the ERAL instruction and any addresses. In this mode, data
does not need to be transferred. After the least significant bit (A0) of the address is received on the
falling edge of SK, an erase operation is triggered by the CS being pulled Low.
CS
Verify
123456789
SK
DI
10010xxxx
DO
Hi-Z
Busy
Ready
t_PW
Hi-Z
Figure 9. Erase Timing Diagram (TC9WMC1)
CS
1 2 3 4 5 6 7 8 9 10 11
SK
Verify
DI
10010xxxxxx
DO
Hi-Z
t_PW
Busy
Ready
Hi-Z
Figure 10. Erase Timing Diagram (TC9WMC2)
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2007-10-19