TC9WMC1FK Datasheet, PDF (2/16 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuits Silicon Monolithic

Block Diagram
Test input
TEST
Chip select: CS
Clock input: SK
Timing
generator
Control
circuit
TC9WMC1FK/FU,TC9WMC2FK/FU
Power supply
(booster circuit)
V_CC power supply
Data input: DI
Data output: DO
Input/output
circuit
Command
register
Address Address
register decoder
Memory cell
GND
Data register
Pin Function
Pin Name
CS
SK
DI
DO
TEST
NC
V_CC
GND
Input/Output
Input
Input
Input
Output
Input
⎯
Power supply
Function
Chip select input
The device receives an instruction set when this pin is driven High.
This pin must be driven Low before execution of an instruction.
Serial clock input
Data is latched on the rising edge of SK. Data is transferred on the rising edge of SK.
This pin is valid when CS is driven High.
Serial data input (start bit, op code, address and data)
Serial data output
Test mode input (internal pull-down resistor)
Normally kept open. (Can be connected to GND.)
No connection (not connected internally)
1.8 to 3.6 V (for reading)
2.3 to 3.6 V (for writing)
0 V (GND)
2
2007-10-19