TC9WMC1FK Datasheet, PDF (10/16 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuits Silicon Monolithic

3. Notes on Use
TC9WMC1FK/FU,TC9WMC2FK/FU
(1) Powering up the device
This device contains a power-on clear circuit, which initializes the internal circuit of the device
when the power is turned on. If initialization fails, the chip may malfunction. When powering up the
device, observe the following precautions to assure that the clear circuit will operate normally:
(a) Pull CS Low.
(b) The power rising time (t_R) must be 10 ms or less.
(c) After turning off the power, wait at least 100 ms (t_OFF) before attempting to power up the
device again.
(d) The supply voltage must rise from a voltage lower than 0.1 V.
(e) After turning on the power, wait at least 20 ms before attempting to send an instruction to the
device.
V_CC
V_CC
0.1 V max
0V
t_OFF
t_R
(2) Dummy cycle
Figure 13
20 ms
When the DI input is driven Low, the SK clock cycles preceding a start bit are called “dummy
cycles”. The device executes dummy cycles when an instruction from the CPU is longer than that for
the device. For example, if the CPU’s instruction is 16 bits long, the TC9WMC1 executes seven
dummy cycles and the TC9WMC2 executes five dummy cycles. Thus, the two instructions take the
same number of clock cycles.
(3) Erroneous detection of a start bit
(a) If the DO output is High during the verify operation, a High on the DI input on the rising edge
of SK causes the device to detect erroneously the start of serial reception. To prevent this, the
DI input must be driven Low during the verify operation.
(b) When the DI and DO pins are configured as a 3-wire interface, data transfer from the CPU and
that from the device can collide with each other during a certain period of time and the device
cannot detect the start of serial reception correctly. To prevent this, a 10- to 100-KΩ resistor
must be inserted between the DI and DO pins, so that the DI input from the CPU takes priority.
(See Figure 14.)
CPU
TC9WMC1
TC9WMC2
SIO
DI
DO
Figure 14
(4) Verify operation
(a) The DI input must be driven Low during the verify operation.
(b) When the DO output is driven High, a High on the DI input on the rising edge of SK causes the
device to detect erroneously the start of serial reception and accepts an instruction. In this case,
the DO pin immediately goes to the high-impedance state.
(5) Instruction cancellation
During an instruction execution, the instruction can be cancelled by pulling the CS pin Low.
However, care must be taken for the timing of canceling a write operation as described below.
(a) The write operation can be cancelled when the CS is pulled Low on the rising edge of SK when
the 15th bit of data is received.
(b) The write operation cannot be cancelled when the CS is pulled Low on the rising edge of SK
after the 17th bit of data is received. In this case, the write instruction writes the 16 bits of data
into the specified memory location.
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2007-10-19