TC9WMC1FK Datasheet, PDF (6/16 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuits Silicon Monolithic

TC9WMC1FK/FU,TC9WMC2FK/FU
(3.3)
Erase (ERASE)
The Erase instruction writes all bits in the specified memory location to 1. After the CS is driven
High, a start bit is transferred followed by the ERASE instruction and address. In this mode, data
does not need to be transferred. After the least significant bit (A0) of the address is received on the
falling edge of SK, an erase operation is triggered by the CS being pulled Low.
CS
Verify
123456789
SK
DI
1 1 1 A5 A4 A3 A2 A1 A0
DO
Hi-Z
Busy
Ready
Hi-Z
t_PW
Figure 5. Erase Timing Diagram (TC9WMC1)
CS
1 2 3 4 5 6 7 8 9 10 11
SK
Verify
DI
1 1 1 x A6 A5 A4 A3 A2 A1 A0
DO
Hi-Z
Busy
Ready
Hi-Z
t_PW
Figure 6. Erase Timing Diagram (TC9WMC2)
6
2007-10-19