TC9WMC1FK Datasheet, PDF (3/16 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuits Silicon Monolithic

1. Instruction Set
Instruction
READ (Read)
WRITE (Write)
ERASE (Erase)
WRAL (Write All)
ERAL (Erase All)
EWEN (Program Enable)
EWDS (Program Disable)
x: Don’t care
Start Bit
1
1
1
1
1
1
1
TC9WMC1FK/FU,TC9WMC2FK/FU
Op Code
10
01
11
00
00
00
00
Address
TC9WMC1 TC9WMC2
A5 to A0
xA6 to A0
A5 to A0
xA6 to A0
A5 to A0
xA6 to A0
01xxxx
01xxxxxx
10xxxx
10xxxxxx
11xxxx
11xxxxxx
00xxxx
00xxxxxx
Data
D15 to D0 outputs
D15 to D0 inputs
⎯
D15 to D0 inputs
⎯
⎯
⎯
2. Functional Description
All instructions are executed when the DI input is received on the rising edge of SK after the CS input is
driven High. An instruction starts with a start bit followed by an op code, address and data bits. The
instruction transfer is completed when the CS input is driven Low. The CS must be driven Low during the
tCS cycle period between instruction transfers. When the CS is Low, the device is in standby mode. The SK
and DI inputs are disabled and the device does not respond to any instructions.
(1) Start bit
After the CS is driven High, a High on the DI input on the rising edge of SK indicates a start bit. A
start bit is not identified if the DI is driven Low even after the CS is driven High and the SK pulse is
applied.
Refer to (2) Dummy cycle in Section 3, Notes on Use.
(2) Read operation (READ)
The Read instruction reads data at specified addresses. After the CS is driven High, a start bit,
READ instruction and address are transferred to the device. After the least significant bit of address
(A0) is received, the DO output changes from high impedance to logic Low on the 9th rising edge of
SK. On the 10th rising edge of SK, the 16 bits of data appear on the DO output.
(2.1)
Sequential read
After the 16 bits of data are driven onto the DO output, the device will automatically increment
the internal address counter and clock out data in the next memory location as long as the CS is
held High and the SK pulse is applied. In this way, data in all the memory locations can be read in
sequence. After the data in the last memory address is read, the address counter rolls over to the
first memory address.
CS
1 2 3 4 5 6 7 8 9 10 11 12
23 24 25 26 27 28
39 40^DI 42
D
SK
DI
1 1 0 A5 A4 A3 A2 A1 A0
DO
Hi-Z
D15 D14 D13
D2 D1 D0 D15 D14 D13
D2 D1 D0 D15
Hi-Z
Figure 1. Read Timing Diagram (TC9WMC1)
3
2007-10-19