TA1310ANG Datasheet, PDF (77/106 Pages) Toshiba Semiconductor – NTSC VIDEO, CHROMA, DEFLECTION, AND DISTORTION COMPENSATION IC (WITH YUV INTERFACE AND ACB)

Deflection stage
NOTE
ITEM
D₁
Sync separation Input
Sensitivity Current
SW MODE
SW₃₄ SW₃₈
OFF B
D₂
V separation Filter Pin
Source Current
OFF B
D₃ V Separation Level
OFF B
H AFC Phase Detection
D₄ Curren H AFC Phase
Detection Current Ratio
OFF A
TA1310ANG
TEST CONDITIONS (DEF V_CC = 9 V, Ta = 25 ± 3°C, BUS DATA = POWER-ON RESET)
MEASUREMENT METHOD
When the number of H periods in the #33 (VD out) waveform changes from 297 to 225, increase the
voltage from 3 V and measure the value at in the diagram.
When the subaddress (0D) D₁ is set to (1), measure the value at in the diagram.
When #38 (Sync in) is connected to GND, measure the #39 (VSEP FILTER) voltage.
Set the voltage to around 7.5 V, equivalent to when #40 (AFC1 FILTER) has no load. When a signal as
shown in the diagram below is input to #38 (Sync in) from TG7, calculate V₁ and V₂ using the #40
waveform.
I_DET = V₁ ÷ 1 kΩ (µA)
∆I_DET = (V₁ / V₂ − 1) × 100 (%)
D₅ Phase Detection Stop Period OFF A Input a composite video signal to #38 and measure the V mask period of the #40 (AFC1 FILTER) waveform.
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2005-09-20