TMPR4956C Datasheet, PDF (76/286 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 3 TX49/H4 Core’s Registers
3.2.12 Cause Register (Reg#13)
The Cause register holds the cause of the most recent exception. This register is read-only, except for
the IP[1:0] bits.
Figure 3.2.12 shows the format of the Cause register and Table 3.2.13 describes the Cause register
field.
31
BD
30 29 28 27
16 15
876
21 0
0
CE
0
IP
0 ExcCode
0
Figure 3.2.12 Cause Register Format
Bit(s)
31
30
29:28
27:16
15:10
9:8
7
6:2
1:0
Table 3.2.13 Cause Register Field Descriptions
Field Name
Description
Cold Reset
BD
0
CE
0
IP[7:2]
IP[1:0]
0
ExcCode
0
Indicates whether or not the last exception was taken while
executing in a branch delay slot.
0: normal
1: delay slot
Reserved
Indicates the coprocessor unit number referenced when a
coprocessor unusable exception is taken.
00: coprocessor 0
01: coprocessor 1
10: coprocessor 2
11: coprocessor 3
Reserved
Indicates whether an interrupt is pending.
0: not pending
1: pending
Software interrupts.
0: reset
1: set
Reserved
Exception Code field.
0: Int: Interrupt.
1: Mod: TLB modification exception.
2: TLBL: TLB exception (load or instruction fetch)
3: TLBS: TLB exception (Store)
4: AdEL: Address error exception (load or instruction fetch)
5: AdES: Address error exception (store)
6: IBE: Bus error exception (instruction fetch)
7: DBE: Bus error exception (data reference: load)
8: Sys: System call exception
9: Bp: Breakpoint exception
10: RI: Reserved instruction exception
11: CpU: Coprocessor Unusable exception
12: Ov: Arithmetic Overflow exception
13: Tr: Trap exception
14: Reserved
15: FPE: Floating-Point exception
16-31: Reserved
Reserved
0
0
0x0
0x0
INT[5:0]
0x0
0
0x0
0x0
Read/Write
Read
Read
Read
Read
Read
Read/Write
Read
Read
Read
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