TMPR4956C Datasheet, PDF (57/286 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 2 Features
Signal Name
JTDI
Pin No.
B4
JTCK
B3
JTDO/TPC[0]
A5
JTMS
C3
DCLK
P12
PCST[8:0]
TPC[3:1]
TRST*
C8, C7, C6,
C5, C4, K3,
L3, M3, N3
N13, M13,
L13
M1
Table 2.2.7 EJTAG Interface
I/O
Function
I
JTAG data input/Debug interrupt input
Run-time mode: Input serial data to JTAG data/instruction registers.
(with pull-up resistor).
I
JTAG clock input
Clock input for JTAG. The JTDI and JTMS data are latched on rising edges of this
clock (with pull-up resistor).
O
JTAG data output/Trace PC output
Data is serially shifted out from this pin. Outputs a non-sequential program counter
value synchronously with DCLK.
I
JTAG command
Controls mainly the status transition of the TAP controller state machine.
When the serial input data is a JTAG command, apply a high signal (= 1) to this pin
(with pull-up resistor).
O
Debug clock (1/3 CPU clock)
Clock output for a real-time debug system. Timings of the serial monitor bus and PC
trace interface signals all are defined by this debug clock DCLK.
DCLK clock frequency is 1/3 that of CPUCLK.
O
PC trace status
Outputs PC trace status information and serial monitor bus mode.
O
Trace PC output (with pull-up resistor for TPC[1] and with pull-down resistors for
TPC[3:2])
Outputs a non-sequential program counter value synchronously with DCLK.
I
Test reset input
Reset input for a real-time debug system. When TRST* is asserted (= 0), the debug
support unit (DSU) is initialized. TRST* should be asserted when DSU is not used
(with pull-down resistor).
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