TMPR4956C Datasheet, PDF (181/286 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 11 TX4956 System Interface
3. At the same time, the processor asserts the ValidOut* signal for one cycle. This means that
valid data are being transmitted to the SysCmd bus and SysAD bus.
4. The processor goes into the slave state by itself either at the issue cycle of a read request or after
the Release* signal is asserted for one cycle and the issue cycle of the read request is complete.
Note: The external agent must not assert the ExtRqst* signal as a means of returning
a read response. It must however wait to shift to the slave state on its own. If an
external request other than a read response is issued, ExtRqst* can be
asserted either before the read response or in the process of the read response.
5. The SysCmd bus and SysAD bus are released from the processor one cycle after the Release*
signal is asserted.
6. The SysCmd bus and SysAD bus are driven by the external agent within two cycles after the
Release* signal is asserted.
When shifting to the slave state (from Cycle 5 in Figure 11.2.12), the external agent can return the
requested data as a read response. Notification of an error in the returned data is sent if either the
data requested by a read response were returned or if the requested data could not be fetched. In this
case, the processor handles the result as a bus error exception.
Figure 11.2.12 illustrates a situation in which the slave state is autonomously shifted to after a
processor read request is issued.
Note: The timing of the SysADC bus and SysCmdP bus are the same as the timing of the
SysAD bus and SysCmd bus timing, respectively.
Master
Slave
Cycle
1
2
3
4
5
6
7
8
9
10
11
12
MasterClock
SysAD Bus
SysCmd Bus
2
ValidOut*
Validln*
RdRdy* ¹
WrRdy*
Release*
Addr
56
Read
3
4
Figure 11.2.12 Processor Read Request Protocol
11-13