TMPR4956C Datasheet, PDF (134/286 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 8 CPU Exception
8.7 Address Error Exception
8.7.1
Cause
The Address Error exception occurs when an attempt is made to execute one of the following.
• load or store a doubleword that is not aligned on a doubleword boundary
• load, fetch or store a word that is not aligned on a word boundary
• load or store a halfword that is not aligned on a halfword boundary
• reference Kernel mode address while in User or Supervisor mode
• reference Supervisor mode address while in User mode
This exception is not maskable.
8.7.2
Processing
The common exception vector (virtual address: 0x8000_0180/0xffff_ffff_8000_0180) is used.
ExcCode AdEL or AdES in Cause register is set depending on whether the memory access attempt was a
load or store. When this exception is raised, the misalign virtual address causing the exception, or the
protected virtual address that was illegally referenced, is placed in BadVAddr register. The contents of the
VPN field of Context and EntryHi registers are undefined, as are the contents of EntryLo register.
If EXL bit of Status register is only set to 0, the following operation is executed. EPC register points to
the address of the instruction causing the exception. If, however, the affected instruction was in the branch
delay slot (for execution during a branch), the immediately preceding branch instruction address is
retained in EPC register and BD bit of Cause register is set to 1.
8.7.3
Servicing
The process executing at the time is handed a segmentation violation signal. This error is usually fatal
to the process incurring the exception.
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