TMPR4956C Datasheet, PDF (120/286 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 5 Cache Organization
5.6 Cache Line Ownership
The processor becomes the owner of a cache line after it writes to that cache line (that is, by entering the
dirty exclusive), and is responsible for providing the contents of that line on a read request. There can only be
one owner for each cache line.
5.7 Cache Multi-Hit Operation
The processor is not guaranteed the operation for the multi-hit of primary cache.
Thus, in case of locking the specified program/data in the primary cache, the program/data must be used
after locked in the cache by Fill instruction.
5.8 FIFO Replacement Algorithm
The instruction and data caches in the processor use the FIFO replacement algorithm.
• Usually, cache elements are replaced in this order: Way0, Way1, Way2, Way3.
• The FIFO[1:0] replacement bits do not point to a locked, valid cache line.
• Data is first written to a cache line marked invalid, if any.
• The FIFO replacement bits change every time memory data is written to the cache or a CACHE
instruction is executed.
Figure 5.8.1 shows several examples of how the FIFO replacement bits change.
Way0 Way1 Way2 Way3
A) Invalid Invalid Invalid Invalid
Way0 Way1 Way2 Way3
B) Invalid ^Invalid Invalid Invalid
Lock
Way0 Way1 Way2 Way3
C) Invalid Invalid valid Invalid
Way0 Way1 Way2 Way3
D) Invalid ^valid
Lock
Invalid valid
Way0 Way1 Way2 Way3
E) Invalid ^valid
Lock
valid
Lock
valid
Lock
Way0 Way1 Way2 Way3
F)
valid
valid
valid
Lock
valid
Figure 5.8.1 Examples of Cache State Transitions by the FIFO Replacement Algorithm
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