TMPR4956C Datasheet, PDF (74/286 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 3 TX49/H4 Core’s Registers
Bit(s)
21
20
19
18
17:16
15:8
7
6
5
4:3
2
1
0
Field Name
Description
0
SR
0
CH
0
IM
KX
SX
UX
KSU
ERL
EXL
IE
Reserved
1: Indicates a soft reset or NMI has occurred.
Reserved
“Hit” or “miss” indication for last CACHE Hit Invalidate, Hit
Write Back Invalidate, Hit Write Back for a primary cache.
0: miss
1: hit
Reserved
Interrupt Mask
Controls the enabling of each of the external, internal and
software interrupts. An interrupt is taken if interrupts are
enabled, and the corresponding bits are set in both the IM field
of the Status register and the IP field of the Cause register.
0: disabled
1: enabled
Enables 64-bit addressing in Kernel mode. The
extended-addressing TLB refill exception is used for TLB
misses on kernel addresses.
0: 32-bit
1: 64-bit
Enables 64-bit addressing and operations in Supervisor
mode. The extended-addressing TLB refill exception is used
for TLB misses on supervisor addresses.
0: 32-bit
1: 64-bit
Enables 64-bit addressing and operations in User mode. The
extended-addressing TLB refill exception is used for TLB
misses on user addresses.
0: 32-bit
1: 64-bit
Mode
10: user
01: supervisor
00: kernel
11: reserved
Error Level
0: normal
1: error
Exception Level
0: normal
1: exception
Interrupt Enable
0: disable
1: enable
Cold Reset
0
0
0
0
0x0
0x0
0
0
0
0x0
1
0
0
Read/Write
Read
Read/Write
Read
Read/Write
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
3-14