TMPR4956C Datasheet, PDF (146/286 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 8 CPU Exception
8.18 Floating-Point Exception
8.18.1 Cause
The Floating-Point exception is used by the floating-point coprocessor. This exception is not maskable.
8.18.2 Processing
The common exception vector is used for this exception, and the FPE code in Cause register is set. The
contents of the Floating-Point Control/Status register indicate the cause of this exception.
If EXL bit of Status register is only set to 0, the following operation is executed. EPC register points to
the address of the instruction causing the exception. If, however, the affected instruction was in the branch
delay slot (for execution during a branch), the immediately preceding branch instruction address is
retained in EPC register and the BD bit of Cause register is set to 1.
8.18.3 Servicing
This exception is cleared by clearing the appropriate bit in the Floating-Point Control/Status register.
For an unimplemented instruction exception, the kernel should emulate the instruction; for other
exceptions, the kernel should pass the exception to the user program that caused the exception.
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