TH50VSF2580AASB Datasheet, PDF (2/50 Pages) Toshiba Semiconductor – SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE

PIN ASSIGNMENT (TOP VIEW)
• CIOF = V_CC, CIOS = V_SS (×16, ×8)
1
2
3
4
5
6
7
8
9
10
A NC
NC
B NC
NC
C NC
A7 DU WP/ACC WE A8 A11
D
A3 A6 DU RESET CE2S A19 A12 A15
E
A2 A5 A18 RY/BY A20 A9 A13 NC
F NC A1 A4 A17
A10 A14 NC NC
G NC A0 V_SS DQ1
H
CEF OE DQ9
DQ3
DQ6 SA A16 NC
DQ4 DQ13 DQ15 CIOF
J
CE1S DQ0 DQ10 V_CCf V_CCs DQ12 DQ7 V_SS
K
DQ8 DQ2 DQ11 CIOS DQ5 DQ14
L NC
NC
M NC
NC
• CIOF = V_SS, CIOS = V_SS (×8, ×8)
1
2
3
4
5
6
7
8
9
10
A NC
NC
B NC
NC
C NC
A7 DU WP/ACC WE A8 A11
D
A3 A6 DU RESET CE2S A20 A13 A16
E
A2 A5 A19 RY/BY A21 A9 A14 NC
F NC A1 A4 A18
A10 A15 NC NC
G NC A0 V_SS DQ1
H
CEF OE DU
DQ3
DQ6 A12S A17 NC
DQ4 DU A12F CIOF
J
CE1S DQ0 DU V_CCf V_CCs DU DQ7 V_SS
K
DU DQ2 DU CIOS DQ5 DU
L NC
NC
M NC
NC
Note: A12F and A12S should be wired together and used as a single A12 pin.
TH50VSF2580/2581AASB
000707EBA2
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
• The information contained herein is subject to change without notice.
2001-10-26 2/50