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TH50VSF2580AASB Datasheet, PDF (18/50 Pages) Toshiba Semiconductor – SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE
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COMMAND WRITE/PROGRAM/ERASE CYCLE
SYMBOL
PARAMETER
tCMD
Command Write Cycle Time
tAS
Address Set-up Time / BYTE Set-up Time
tAH
Address Hold Time / BYTE Hold Time
tAHW
Address Hold Time from WE High level
tDS
Data Set-up Time
tDH
Data Hold Time
tWELH
WE Low-Level Hold Time
( WE Control)
tWEHH
WE High-Level Hold Time
( WE Control)
tCES
CEF Set-up Time to WE Active ( WE Control)
tCEH
CEF Hold Time from WE High Level
( WE Control)
tCELH
CEF Low-Level Hold Time
( CEF Control)
tCEHH
CEF High-Level Hold Time
( CEF Control)
tWES
WE Set-up time to CEF Active ( CEF Control)
tWEH
WE Hold Time from CEF High Level
( CEF Control)
tOES
OE Set-up Time
tOEHP
OE Hold Time (Toggle, Data Polling)
tOEHT
OE High-Level Hold Time (Toggle)
tAST
Address Set-up Time (Toggle)
tAHT
Address Hold Time (toggle)
tBEH
Erase Hold Time
tVCS
VCCf Set-up Time
tBUSY
Program/Erase Valid to RY/BY Delay
tRP
RESET Low-Level Hold Time
tREADY RESET Low-Level to Read Mode
tRB
RY/BY Recovery Time
tRH
RESET Recovery Time
tCEBTS CEF Set-up time BYTE Transition
tSUSP
Program Suspend Command to Suspend Mode
tRESP
Program Resume Command to Program Mode
tSUSE
Erase Suspend Command to Suspend Mode
tRESE
Erase Resume Command to Erase Mode
TH50VSF2580/2581AASB
MIN
MAX
UNIT
120

ns
0

ns
50

ns
20

ns
50

ns
0

ns
50

ns
20

ns
0

ns
0

ns
50

ns
20

ns
0

ns
0

ns
0

ns
90

ns
20

ns
0
ns
0
ns
50

µs
500

µs

90
ns
500

ns

20
µs
0

ns
50

ns
5

ns

1.5
µs

1
µs

15
µs

1
µs
2001-10-26 18/50
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