TMS320DM640AZNZ4 Datasheet, PDF (99/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

3.3 V
EMI
filter
CLKMODE0
CLKMODE1
CLKIN
C1 C2
10 μF 0.1 μF
PLLV
PLLMULT
PLL
x6, x12
PLLCLK 1
0
Clock PLL
CPU Clock
/2
Peripheral Bus, EDMA
Clock
/8
Timer Internal Clock
CLKOUT4, Peripheral Clock
/4
(AUXCLK for McASP),
McBSP Internal Clock
/6
CLKOUT6
00 01 10
/4
ECLKIN
AEA[20:19]
Internal to DM641/DM640
/2
EMIF
00 01 10
EK2RATE
(GBLCTL.[19,18])
(For the PLL Options, CLKMODE Pins Setup, and
PLL Clock Frequency Ranges, see Table 9.)
ECLKOUT1 ECLKOUT2
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000™ DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV_DD.
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 4−12. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
June 2003 − Revised October 2010
SPRS222F
99