TMS320DM640AZNZ4 Datasheet, PDF (111/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

External Memory Interface (EMIIF)
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:3]
AED[31:0]
Write
Latency =
1^‡
1
1
2
BE1
4
EA1
10
BE2
EA2
10
Q1
BE3
EA3
Q2
3
BE4
5
EA4
11
Q3
Q4
8
8
AARE/ASDCAS/ASADS/
ASRE^§
AAOE/ASDRAS/ASOE^§
12
12
AAWE/ASDWE/ASWE^§
† _{The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space}
Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0.
‡ _{The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):}
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
§ _{AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,}
respectively, during programmable synchronous interface accesses.
Figure 4−23. Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 1)^†‡
June 2003 − Revised October 2010
SPRS222F 111