TMS320DM640AZNZ4 Datasheet, PDF (140/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

Multichannel Buffered Serial Port (McBSP)
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
1
2
3
3
4
4
5
6
7
2
3
3
Bit(n-1)
9
8
(n-2)
11
10
12
Bit 0
14
13^†
Bit(n-1)
13^†
(n-2)
† _{Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.}
(n-3)
(n-3)
Figure 4−44. McBSP Timing
Table 4−45. Timing Requirements for FSR When GSYNC = 1 (see Figure 4−45)
NO.
1
t_su(FRH-CKSH)
2
t_h(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
−400
−500
−600
MIN MAX
4
4
UNIT
ns
ns
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
1
2
Figure 4−45. FSR Timing When GSYNC = 1
140 SPRS222F
June 2003 − Revised October 2010