TMS320DM640AZNZ4 Datasheet, PDF (97/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

Reset
CLKOUT4
CLKOUT6
1
RESET
2
3
AECLKIN
4
5
AECLKOUT1
AECLKOUT2
6
7
EMIF Z Group^†‡
8
9
EMIF High Group^†
10
11
EMIF Low Group^†
12
13
Low Group^†
14
Z Group^†‡
Boot and Device
Configuration Inputs^§
15
16
17
† _{EMIF Z group consists of: AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,}
AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT.
EMIF high group consists of: AHOLDA (when the corresponding AHOLD input is high)
EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding AHOLD input is low)
Low group consists of:
Z group consists of:
HD[15:0], VP0D[0]/CLKX0, VP0D[1]/FSX0, VP0D[2]/DX0, CLKR0, VP0D[5]/FSR0, TOUT0, TOUT1, VDAC,
GP0[7:0], HR/W, HDS2, HDS1, HCS, HCNTL1, HAS, HCNTL0, HHWIL (16-bit HPI mode only), HRDY, HINT, and
VP0D[4,3].
VP1 signals apply to DM641 only:
VP1D[0]/CLKX1, VP1D[1]/FSX1, VP1D[2]/DX1, VP1D[6]/CLKR1, VP1D[5]/FSR1, and VP1D[4,3].
‡ _{If AEA[22:19], LENDIAN, and HD5 pins are actively driven, care must be taken to ensure}
no timing contention between parameters 6, 7, 14, 15, 16, and 17.
§ _{Boot and Device Configurations Inputs (during reset) include: AEA[22:19], LENDIAN, and HD5.}
Figure 4−11. Reset Timing^†
June 2003 − Revised October 2010
SPRS222F
97